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ics9fg108d idt tm frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 1542e 12/16/10 frequency generator for cpu, qpi, fbd, pcie gen 2 & sata datasheet 1 description ics9fg108d is a frequency timing generator that provides 8 differential output pairs that are compliant to the intel ck410 specification. it also provides support for pci-express, next generation i/o, and sata. the part synthesizes several output frequencies from either a 14.31818 mhz crystal or a 25 mhz crystal. the device can also be driven by a reference input clock instead of a crystal. it provides outputs with cycle-to-cycle jitter of less than 50 ps and output-to-output skew of less than 65 ps. ics9fg108d also provides a copy of the reference clock. frequency selection can be accomplished via strap pins or smbus control. key specifications ? output cycle-to-cycle jitter < 50 ps ? output to output skew < 65 ps ? +/-300 ppm frequency accuracy on output clocks ? +/-50 ppm at any frequency with spread off features/benefits ? generates common frequencies from 14.318 mhz or 25 mhz ? crystal or reference input ? 8 - 0.7v current-mode differential output pairs ? supports serial-ata at 100 mhz ? two spread spectrum modes: 0 to -0.5 down spread and +/-0.25% center spread ? unused inputs may be disabled in either driven or hi-z state for power management. functional block diagram stop logic xin/clkin x2 dif(7:0) control logic spread fs(2:0) sdata sclk sel14m_25m# dif_stop# programmable spread pll 8 iref osc r e f o u t oe(7:0)
idt tm frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 1542e 12/16/10 ics9fg108d frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 2 pin configuration functionality table power groups 48-pin ssop & tssop frequency select table sel14m_25m# (fs3) fs2 fs1 fs0 output(mhz) 0 0 0 0 100.00 0 0 0 1 125.00 0 0 1 0 133.33 0 0 1 1 166.67 0 1 0 0 200.00 0 1 0 1 266.66 0 1 1 0 333.33 0 1 1 1 400.00 1 0 0 0 100.00 1 0 0 1 125.00 1 0 1 0 133.33 1 0 1 1 166.67 1 1 0 0 200.00 1 1 0 1 266.66 1 1 1 0 333.33 1 1 1 1 400.00 vdd gnd 34 10,14,19,31,36,40 15,35 n/a 47 48 47 iref analog vdd & gnd for pll core descri p tion pin number refout, digital inputs, smbus dif outputs xin/clkin 1 48 vdda x2 2 47 gnda vdd 3 46 iref gnd 4 45 vfs0 refout 5 44 vfs1 vfs2 6 43 voe_0 voe_7 7 42 dif_0 dif_7 8 41 dif_0# dif_7# 9 40 vdd vdd 10 39 dif_1 dif_6 11 38 dif_1# dif_6# 12 37 ^oe_1 ^oe_6 13 36 vdd vdd 14 35 gnd gnd 15 34 ^oe_2 ^oe_5 16 33 dif_2 dif_5 17 32 dif_2# dif_5# 18 31 vdd vdd 19 30 dif_3 dif_4 20 29 dif_3# dif_4# 21 28 voe_3 voe_4 22 27 ^sel14m_25m# sdata 23 26 vspread sclk 24 25 dif_stop# ics9fg108d ^ indicates internal 120k pull up v indicates internal 120k pull down
idt tm frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 1542e 12/16/10 ics9fg108d frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 3 pin description pin # pin name pin type description 1 xin/clkin in crystal input or reference clock input 2 x2 out crystal output, nominally 14.318mhz 3 vdd pwr power supply, nominal 3.3v 4 gnd pwr ground pin. 5 refout out reference clock output 6 vfs2 in frequency select pin. this pin has an internal 120k pull down resistor 7voe_7 in active high input for enabling output 7. this pin has a 120kohm pull down. 0 = tri-state outputs, 1= enable outputs 8 d if_ 7 ou t 0 .7v differe ntial true clock o utpu t 9 dif_7# out 0.7v differential complementary clock output 10 vdd pwr power supply, nominal 3.3v 11 dif_6 out 0.7v differential true clock output 12 dif_6# out 0.7v differential complementary clock output 13 ^oe_6 in active high input for enabling output 6. this pin has an internal 120kohm pull up. 0 = tri-state outputs, 1= enable outputs 14 vdd pwr power supply, nominal 3.3v 15 gnd pwr ground pin. 16 ^oe_5 in active high input for enabling output 5. this pin has an internal 120kohm pull up. 0 = tri-state outputs, 1= enable outputs 17 dif_5 out 0.7v differential true clock output 18 dif_5# out 0.7v differential complementary clock output 19 vdd pwr power supply, nominal 3.3v 20 dif_4 out 0.7v differential true clock output 21 dif_4# out 0.7v differential complementary clock output 22 voe_4 in active high input for enabling output 4. this pin as an internal 120kohm pull down. 0 = tri-state outputs, 1= enable outputs 2 3 sd ata i/o d a ta pin fo r smbus circuitry, 3.3v tolerant. 24 sclk in clock pin of smbus circuitry, 5v tolerant. note: ^ indicates internal 120k pull up v indicates internal 120k pull down
idt tm frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 1542e 12/16/10 ics9fg108d frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 4 pin description (continued) pin # pin name pin type description 25 dif_stop# in active low input to stop differential output clocks. 26 vspread in asynchronous, active high input to enable spread spectrum functionality. this pin has a 120kohm pull down resistor. 27 ^sel14m_25m# in select 14.31818 mhz or 25 mhz input frequency. this pin has an internal 120kohm pull up resistor. 1 = 14.31818 mhz, 0 = 25 mhz 28 voe_3 in active high input for enabling output 3. this pin has an internal 120kohm pull down resistor. 0 = tri-state outputs, 1= enable outputs 29 dif_3# out 0.7v differential complementary clock output 30 dif_3 out 0.7v differential true clock output 31 vdd pwr power supply, nominal 3.3v 32 dif_2# out 0.7v differential complementary clock output 33 dif_2 out 0.7v differential true clock output 34 ^oe_2 in active high input for enabling output 2. this pin has in internal 120kohm pull up resistor. 0 = tri-state outputs, 1= enable outputs 35 gnd pwr ground pin. 36 vdd pwr power supply, nominal 3.3v 37 ^oe_1 in active high input for enabling output 1. this pin has an internal 120kohm pull up resistor. 0 = tri-state outputs, 1= enable outputs 38 dif_1# out 0.7v differential complementary clock output 39 dif_1 out 0.7v differential true clock output 40 vdd pwr power supply, nominal 3.3v 41 dif_0# out 0.7v differential complementary clock output 42 dif_0 out 0.7v differential true clock output 43 voe_0 in active high input for enabling output 0. this pin has an internal 120kohm pull down resistor. 0 = tri-state outputs, 1= enable outputs 44 vfs1 in 3.3v frequency select latched input pin with internal 120kohm pull down resistor. 45 vfs0 in 3.3v frequency select latched input pin with internal 120kohm pull down resistor. 46 iref out this pin establishes the reference current for the differential current-mode output pairs. this pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. 47 gnda pwr ground pin for the pll core. 48 vdda pwr 3.3v power for the pll core. note: ^ indicates internal 120k pull up v indicates internal 120k pull down
idt tm frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 1542e 12/16/10 ics9fg108d frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 5 absolute max electrical characteristics - ref-14.318/25 mhz parameter symbol conditions min typ max units notes long accuracy ppm see tperiod min-max values ppm 1 clock period t p eriod 14.318mhz output nominal ns 1,2 clock period t p eriod 25.000mhz output nominal ns 1,2 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 output high current i oh v oh @min = 1.0 v, v oh @max = 3.135 v -29 -23 ma 1 output low current i ol v ol @min = 1.95 v, v ol @max = 0.4 v 29 27 ma 1 t rf1com v ol = 0.4 v, v oh = 2.4 v commercial temp 0.5 0.8 2 ns 1 t rf1ind v ol = 0.4 v, v oh = 2.4 v industrial temp 0.5 0.8 2 ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 jitter t jcyc-cyccom v t = 1.5 v (commerical) 150 200 ps 1 jitter t jcyc-cycind vt = 1.5 v (industrial) 250 400 ps 1 1 guaranteed by design and characterization, not 100% tested in production. 0 69.8413 40.0000 2 all long term accuracy and clock period specifications are guaranteed assuming that ref is at 14.31818 or 25.00 mhz t a = tambient, supply voltage vdd = 3.3 v +/-5%; r s =33 ? , c l = 5pf (unless otherwise specified) spec rise/fall time electrical characteristics - differential phase jitter parameters parameter symbol conditions min typ max units notes t jp hasepll pcie gen 1 30 86 ps (p-p) 1,2 t jphaselo pcie gen 2 10khz < f < 1.5mhz 1.2 3 ps (rms) 1,2 t jphasehigh pcie gen 2 1.5mhz < f < nyquist (50mhz) 2.2 3.1 ps (rms) 1,2 t jphqpi qpi 133mhz 4.8g/6.4gb,12ui 0.26/ 0.18 0.5 ps (rms) 1,3 t jphfbd3.2g fbd specs (11 to 33mhz) 1.8 3 ps (rms) 1 t jphfbd4.8g fbd specs (11 to 33mhz) 1.4 2.5 ps (rms) 1 1 guaranteed by desi g n and characterization, not 100% tested in production. 2 see htt p ://www. p cisi g .com for com p elte s p ecs 3 first number is 4.8g link s p eed , second number is 6.4g link s p eed. from intel clock jit tool 1.5.1 jitter, phase spec t a = commercial and industrial, supply volta g e vdd = 3.3 v +/-5% symbol parameter min max units vdd_a 3.3v core supply voltage 4.6 v vdd 3.3v logic supply voltage 4.6 v ts storage temperature -65 150 c tambient ambient operating temp?(commerical grade) 0 +70 c tambient ambient operating temp?(industrial grade) -40 +85 c tcase case temperature 115 c esd prot input esd protection?human body model 2000 v
idt tm frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 1542e 12/16/10 ics9fg108d frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 6 electrical characteristics - input/supply/common output parameters t a = tambient, supply voltage v dd = 3.3 v +/-5% parameter symbol conditions min typ max units notes input high voltage v ih 3.3 v +/-5% 2 v dd + 0.3 v1 input low voltage v il 3.3 v +/-5% v ss - 0.3 0.8 v 1 input high current i ih v in = v dd -5 5 ua 1 i il1 v in = 0 v; inputs with no pull- up resistors -5 ua 1 i il2 v in = 0 v; inputs with pull-up resistors -200 ua 1 idd vdd 186 215 ma 1 idd vdda 22 25 ma 1 idd vdd 156 179 ma 1 idd vdda 22 25 ma 1 idd vddpd 148 170 ma 1 idd vddapd 22 25 ma 1 idd vddpd 30 35 ma 1 idd vddapd 22 25 ma 1 idd vdd 205 236 ma 1 idd vdd 24 28 ma 1 idd vdda 172 198 ma 1 idd vdda 24 28 ma 1 163 187 ma 1 24 28 ma 1 33 38 ma 1 24 28 ma 1 sel14m_25m# = 0 22.50 25.00 28.00 mhz 3 sel14m_25m# = 1 12.89 14.31818 15.75 mhz 3 pin inductance 1 l p in 7nh1 c in logic inputs 1.5 5 pf 1 c ou t output pin capacitance 6 pf 1 t stabcom from v dd power-up to 1st clock 1.8 ms 1,2 t stabind from v dd power-up to 1st clock 3ms1,2 sel14m_25m# = 0 32.541 khz 1,3,4 sel14m_25m# = 1 32.467 khz 1,3,4 spread modulation % f mod%dwn down spread selected -0.5 % 1,3,4 spread modulation % f mod%ct r center spread selected +/-0.25 % 1,3,4 dif output enable t difoe dif output enable after dif_stop# de-assertion 15 ns 1 input rise and fall times t r /t f 20% to 80% of vdd 5 ns 1 1 guaranteed by desi g n and characterization, not 100% tested in production. 2 see timing diagrams for timing requirements. all dif pairs stopped in hi-z mode 3 input frequency should be measured at the ref pin and tuned to 0 ppm to meet ppm frequency accuracy on pll outputs. 4 these values assume 25mhz or 14.31818mhz inputs respectively. using a higher or lower frequency w ill scale these frequencies accordingly. the output frequecy selected by the fs inputs w ill also scale. for example, 27mhz input with an fs selection of 100mhz will yield an output frequency of 27/25 x 100 = 108mhz. all dif pairs stopped in hi-z mode c l =full load; fout = 400 mhz c l =full load; fout = 100 mhz all dif pairs stopped in driven mode input/output capacitance 1 f i clk stabilization 1,2 input low current operating supply current (t a = commercial) dif_stop# current (t a = commercial) input frequency 3 c l =full load; fout = 400 mhz c l =full load; fout = 100 mhz all dif pairs stopped in driven mode idd vddpd idd vddapd spec operating supply current (t a = industrial) dif_stop# current (t a = industrial) f mod spread modulation frequency
idt tm frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 1542e 12/16/10 ics9fg108d frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 7 electrical characteristics - dif 0.7v current mode differential pair parameter symbol conditions min typ max units notes current source output impedance zo 1 v o = v x 3000 ? 1 voltage high vhigh 660 850 1 voltage low vlow -150 150 1 max volta g e vovs 1150 1 min volta g e vuds -300 1 crossing voltage (abs) vcross(abs) 250 550 mv 1 crossing voltage (var) d-vcross crossing variation over all edges 140 mv 1 14.3m input, ss off -300 300 ppm 1,2,5 14.3m input, ss on -300 300 ppm 1,2,5 25m input ss off -50 50 ppm 1,2,5 25m input, ss on -300 300 ppm 1,2,5 400mhz nominal 2.4993 2.5008 ns 2 400mhz spread 2.4993 2.5133 ns 2,3 333.33mhz nominal 2.9991 3.0009 ns 2 333.33mhz spread 2.9991 3.016 ns 2,3 266.66mhz nominal 3.7489 3.7511 ns 2 266.66mhz spread 3.7489 3.77 ns 2,3 200mhz nominal 4.9985 5.0015 ns 2 200mhz spread 4.9985 5.0266 ns 2,3 166.66mhz nominal 5.9982 6.0018 ns 2 166.66mhz spread 5.9982 6.0320 ns 2,3 133.33mhz nominal 7.4978 7.5023 ns 2 133.33mhz spread 7.4978 5.4000 ns 2,3 100.00mhz nominal 9.9970 10.0030 ns 2 100.00mhz spread 9.9970 10.0533 ns 2,3 400mhz nominal/spread 2.4143 ns 1,2 333.33mhz nominal/spread 2.9141 ns 1,2 266.66mhz nominal/spread 3.6639 ns 1,2 200mhz nominal/spread 4.8735 ns 1,2 166.66mhz nominal/spread 5.8732 ns 1,2 133.33mhz nominal/spread 7.3728 ns 1,2 100.00mhz nominal/spread 9.8720 ns 1,2 rise time t r v ol = 0.175v, v oh = 0.525v 175 700 ps 1 fall time t f v oh = 0.525v v ol = 0.175v 175 700 ps 1 rise time variation d-t r 125 ps 1 fall time variation d-t f 125 ps 1 duty cycle d t3 measured differentially 45 55 % 1 t sk3com t a = commercial, v t =50% 50 ps 1 t sk3ind t a = industrial, v t =50% 65 ps 1 jitter, cycle to cycle t jcyc-cyc measurement from differential wavefrom 50 ps 1 1 guaranteed b y desi g n and characterization, not 100% tested in production. 3 fi g ures are for down spread. ppm t a = tambient, supply voltage vdd = 3.3 v +/-5%, c l =2pf, r s =33.2 ? , r p =49.9 ? , i ref = 475 ? spec long accuracy statistical measurement on single ended signal using oscilloscope math function. average period tperiod skew, output to output absolute min period mv measurement on single ended si g nal usin g absolute value. mv t absmin 5 +/- 50 pp m at an y fre q uenc y with s p read off 4 this figure is the peak-to-peak phase jitter as defined by pci-sig for a pci express reference clock. please visit http://www.pcisi g .com for additional details 2 all long term accuracy and clock period specifications are guaranteed assuming that refout is at 14.31818mhz or 25 mhz
idt tm frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 1542e 12/16/10 ics9fg108d frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 8 general smbus serial interface information for the ics9fg108d how to write: ? controller (host) sends a start bit. ? controller (host) sends the write address dc (h) ? ics clock will acknowledge ? controller (host) sends the begining byte location = n ? ics clock will acknowledge ? controller (host) sends the data byte count = x ? ics clock will acknowledge ? controller (host) starts sending byte n through byte n + x -1 ? ics clock will acknowledge each byte one at a time ? controller (host) sends a stop bit how to read: ? controller (host) will send start bit. ? controller (host) sends the write address dc (h) ? ics clock will acknowledge ? controller (host) sends the begining byte location = n ? ics clock will acknowledge ? controller (host) will send a separate start bit. ? controller (host) sends the read address dd (h) ? ics clock will acknowledge ? ics clock will send the data byte count = x ? ics clock sends byte n + x -1 ? ics clock sends byte 0 through byte x (if x (h) was written to byte 8) . ? controller (host) will need to acknowledge each byte ? controllor (host) will send a not acknowledge bit ? controller (host) will send a stop bit ics (slave/receiver) t wr ack ack ack ack ack p byte n + x - 1 data byte count = x beginning byte n stop bit x byte index block write operation slave address dc (h) beginning byte = n write start bit controller (host) t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit slave address dd (h) index block read operation slave address dc (h) beginning byte = n ack ack data byte count = x ack ics (slave/receiver) controller (host) x byte ack ack
idt tm frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 1542e 12/16/10 ics9fg108d frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 9 smbus table: device control register, read/write address (dc/dd) pin # name control function t yp e 0 1 defaul t bit 7 rw pin 27 bit 6 rw pin 5 bit 5 rw pin 44 bit 4 rw pin 7 bit 3 rw off on pin 26 bit 2 rw hardware select software select 0 bit 1 rw driven hi-z 0 bit 0 rw down center 0 notes: 1. these bits reflect the state of the corresponding pins at power up, but may be written to if byte 0, bit 2 is set to '1'. fs3 is the sel14m_25m# pin. smbus table: output enable register pin # name control function t yp e 0 1 defaul t bit 7 dif_7 en output enable rw disable enable 1 bit 6 dif_6 en output enable rw disable enable 1 bit 5 dif_5 en output enable rw disable enable 1 bit 4 dif_4 en output enable rw disable enable 1 bit 3 dif_3 en output enable rw disable enable 1 bit 2 dif_2 en output enable rw disable enable 1 bit 1 dif_1 en output enable rw disable enable 1 bit 0 dif_0 en output enable rw disable enable 1 note: smbus table: output stop mode register pin # name control function t yp e 0 1 defaul t bit 7 dif_7 stop en free run/ stop enable rw free-run stop-able 0 bit 6 dif_6 stop en free run/ stop enable rw free-run stop-able 0 bit 5 dif_5 stop en free run/ stop enable rw free-run stop-able 0 bit 4 dif_4 stop en free run/ stop enable rw free-run stop-able 0 bit 3 dif_3 stop en free run/ stop enable rw free-run stop-able 0 bit 2 dif_2 stop en free run/ stop enable rw free-run stop-able 0 bit 1 dif_1 stop en free run/ stop enable rw free-run stop-able 0 bit 0 dif_0 stop en free run/ stop enable rw free-run stop-able 0 44 7 b y te 0 27 5 26 spread enable 1 - enable software control of frequency, spread enable (spread type always software control) - dif_stop# drive mode - spread type b y te 1 - - - - - - - - b y te 2 - - byte 1 sets outputs active or inactive, not the conditons set by the oe inputs. - - - - see frequency selection table, page 1 fs3 1 fs2 1 fs1 1 fs0 1 - -
idt tm frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 1542e 12/16/10 ics9fg108d frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 10 smbus table: frequency select readback register pin # name control function t yp e 0 1 defaul t bit 7 sel14m_25m# 1 (fs3) state of pin 27 r pin 27 bit 6 fs2 1 state of pin 6 r pin 6 bit 5 fs1 1 state of pin 44 r pin 44 bit 4 fs0 1 state of pin 45 r pin 45 bit 3 spread 1 state of pin 26 r off on pin 26 bit 2 rx bit 1 rx bit 0 rx notes: 1. these bits reflect the state of the corresponding pins, regardless of whether software programming is enabled or not. smbus table: vendor & revision id register pin # name control function t yp e 0 1 defaul t bit 7 rid3 r - - x bit 6 rid2 r - - x bit 5 rid1 r - - x bit 4 rid0 r - - x bit 3 vid3 r - - 0 bit 2 vid2 r - - 0 bit 1 vid1 r - - 0 bit 0 vid0 r - - 1 smbus table: device id pin # name control function t yp e 0 1 defaul t bit 7 devid7 r 0 bit 6 devid6 r 0 bit 5 devid5 r 0 bit 4 devid4 r 0 bit 3 devid3 r 1 bit 2 devid2 r 0 bit 1 devid1 r 0 bit 0 devid0 r 0 device id = 08 hex reserved reserved reserved reserved reserved reserved reserved reserved b y te 3 6 27 45 44 see frequency selection table, page 1 26 reserved reserved reserved reserved reserved reserved b y te 4 - revision id - - - - - vendor id - - - - - - - b y te 5 - - -
idt tm frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 1542e 12/16/10 ics9fg108d frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 11 smbus table: byte count register pin # name control function t yp e 0 1 defaul t bit 7 bc7 rw - - 0 bit 6 bc6 rw - - 0 bit 5 bc5 rw - - 0 bit 4 bc4 rw - - 0 bit 3 bc3 rw - - 0 bit 2 bc2 rw - - 1 bit 1 bc1 rw - - 1 bit 0 bc0 rw - - 1 smbus table: reserved register pin # name control function t yp e 0 1 defaul t bit 7 x bit 6 x bit 5 x bit 4 x bit 3 x bit 2 x bit 1 x bit 0 x smbus table: reserved register pin # name control function t yp e 0 1 defaul t bit 7 x bit 6 x bit 5 x bit 4 x bit 3 x bit 2 x bit 1 x bit 0 x smbus table: m/n programming enable pin # name control function t yp e 0 1 defaul t bit 7 m/n_en pll m/n programming enable rw disable enable 0 bit 6 oe_polarity select polarity of oe inputs rw oe# oe 1 bit 5 refout_en enables/disables ref rw disable enable 1 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 b y te 6 writing to this register will configure how many bytes will be read back, default is 07 = 7 bytes. - - - - - - - - 5 reserved b y te 9 - - reserved reserved reserved reserved b y te 7 reserved reserved reserved reserved reserved reserved b y te 8 reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved
idt tm frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 1542e 12/16/10 ics9fg108d frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 12 smbus table: pll frequency control register pin # name control function t yp e 0 1 defaul t bit 7 pll n div8 n divider prog bit 8 rw x bit 6 pll n div9 n divider prog bit 9 rw x bit 5 pll m div5 rw x bit 4 pll m div4 rw x bit 3 pll m div3 rw x bit 2 pll m div2 rw x bit 1 pll m div1 rw x bit 0 pll m div0 rw x smbus table: pll frequency control register pin # name control function t yp e 0 1 defaul t bit 7 pll n div7 rw x bit 6 pll n div6 rw x bit 5 pll n div5 rw x bit 4 pll n div4 rw x bit 3 pll n div3 rw x bit 2 pll n div2 rw x bit 1 pll n div1 rw x bit 0 pll n div0 rw x smbus table: pll spread spectrum control register pin # name control function t yp e 0 1 defaul t bit 7 pll ssp7 rw x bit 6 pll ssp6 rw x bit 5 pll ssp5 rw x bit 4 pll ssp4 rw x bit 3 pll ssp3 rw x bit 2 pll ssp2 rw x bit 1 pll ssp1 rw x bit 0 pll ssp0 rw x smbus table: pll spread spectrum control register pin # name control function t yp e 0 1 defaul t bit 7 0 bit 6 pll ssp14 rw x bit 5 pll ssp13 rw x bit 4 pll ssp12 rw x bit 3 pll ssp11 rw x bit 2 pll ssp10 rw x bit 1 pll ssp9 rw x bit 0 pll ssp8 rw x b y te 10 - the decimal representation of m and n divider in byte 11 and 12 will configure the pll vco frequency. default at power up = latch-in or byte 0 rom table. vco frequency = fxtal x [ndiv(9:0)+8] / [ mdiv ( 5:0 ) +2 ] - - m divider programming bit (5:0) - - - - - b y te 11 - the decimal representation of m and n divider in byte 11 and 12 will configure the pll vco frequency. default at power up = latch-in or byte 0 rom table. vco frequency = fxtal x [ndiv(9:0)+8] / [ mdiv ( 5:0 ) +2 ] - - - - - - - b y te 12 - - n divider programming byte11 bit(7:0) and byte10 bit(7:6) - - spread spectrum programming bit(7:0) these spread spectrum bits in byte 13 and 14 will program the spread pecentage of pll - - - - b y te 13 - reserved - - - spread spectrum programming bit(14:8) these spread spectrum bits in byte 13 and 14 will program the spread pecentage of pll - - - -
idt tm frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 1542e 12/16/10 ics9fg108d frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 13 asserting dif_stop# pin stops all dif outputs that are set to be stoppable after their next transition. when the smbus dif_stop tri-state bit corresponding to the dif output of interest is programmed to a '0', dif output will stop dif_true = high and dif_complement = low. when the smbus dif_stop tri-state bit corresponding to the dif output of interest is programmed to a '1', dif outputs will be tri-stated. dif_stop# - assertion (transition from '1' to '0') with the de-assertion of dif_stop# all stopped dif outputs will resume without a glitch. the maximum latency from the de-assertion to active outputs is 2 - 6 dif clock periods. if the control register tristate bit corresponding to the output of interest is programmed to '1', then the stopped dif outputs will be driven high within 15ns of dif_stop# de-assertion to a voltage greater than 200mv. dif_stop# - de-assertion (transition from '0' to '1') dif_stop# dif dif# dif_stop# tdrive_dif_stop, 15ns >200mv dif dif# dif internal
idt tm frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 1542e 12/16/10 ics9fg108d frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 14 common recommendations for differential routing dimension or value unit figure l1 length, route as non-coupled 50ohm trace 0.5 max inch 1 l2 length, route as non-coupled 50ohm trace 0.2 max inch 1 l3 length, route as non-coupled 50ohm trace 0.2 max inch 1 rs 33 ohm 1 rt 49.9 ohm 1 down device differential routing l4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max inch 1 l4 length, route as coupled stripline 100ohm differential trace 1.8 min to 14.4 max inch 1 differential routing to pci express connector l4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max inch 2 l4 length, route as coupled stripline 100ohm differential trace 0.225 min to 12.6 max inch 2 dif reference clock hcsl output buffer l1 l1' rs l2 l2' rs l4' l4 l3 l3' rt rt pci express down device ref_clk input figure 1: down device routing hcsl output buffer l1 l1' rs l2 l2' rs l4' l4 l3 l3' rt rt pci express add-in board ref_clk input figure 2: pci express connector routing
idt tm frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 1542e 12/16/10 ics9fg108d frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 15 vdiff vp-p vcm r1 r2 r3 r4 note 0.45v 0.22v 1.08 33 150 100 100 0.58 0.28 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ics874003i-02 input compatible 0.60 0.3 1.2 33 174 140 100 standard lvds r1a = r1b = r1 r2a = r2b = r2 alternative termination for lvds and other common differential signals (figure 3) hcsl output buffer l1 l1' r1b l2 l2' r1a l4' l4 l3 r2a r2b down device ref_clk input figure 3 l3' r3 r4 component value note r5a, r5b 8.2k 5% r6a, r6b 1k 5% cc 0.1 f vcm 0.350 volts cable connected ac coupled application (figure 4) pcie device ref_clk input figure 4 r5a l4' l4 3.3 volts r5b r6a r6b cc cc
idt tm frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 1542e 12/16/10 ics9fg108d frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 16 index area index area 1 2 n d h x 45 e1 e e - c - b .10 (.004) c .10 (.004) c c l min max min max a 2.41 2.80 .095 .110 a1 0.20 0.40 .008 .016 b 0.20 0.34 .008 .0135 c 0.13 0.25 .005 .010 d e 10.03 10.68 .395 .420 e1 7.40 7.60 .291 .299 e h 0.38 0.64 .015 .025 l 0.50 1.02 .020 .040 n 0 8 0 8 variations min max min max 48 15.75 16.00 .620 .630 10-0034 reference doc.: jedec publication 95, mo-118 48-lead 300 mil ssop n see variations see variations d mm. d (inch) symbol see variations see variations 0.635 basic 0.025 basic common dimensions in millimeters in inches common dimensions 48-pin ssop package outline and dimensions
idt tm frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 1542e 12/16/10 ics9fg108d frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 17 index area index area 12 1 2 n d e1 e seating plane seating plane a1 a a2 e -c- - c - b c l aaa c min max min max a -- 1.20 -- .047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 d e e1 6.00 6.20 .236 .244 e l 0.45 0.75 .018 .030 n 0 8 0 8 aaa -- 0.10 -- .004 variations min max min max 48 12.40 12.60 .488 .496 10-0039 reference doc.: jedec publication 95, mo-153 in millimeters in inches common dimensions 0.50 basic 0.020 basic 8.10 basic 0.319 basic n d (inch) see variations see variations d mm. 48-lead, 6.10 mm. body, 0.50 mm. pitch tssop (240 mil) (20 mil) symbol see variations common dimensions see variations 48-pin tssop package outline and dimensions ordering information part / order number shipping packaging package temperature 9fg108dflf tubes 48-pin ssop 0 to +70c 9fg108dflft tape and reel 48-pin ssop 0 to +70c 9FG108DFILF tubes 48-pin ssop -40 to +85c 9FG108DFILFt tape and reel 48-pin ssop -40 to +85c 9fg108dglf tubes 48-pin tssop 0 to +70c 9fg108dglft tape and reel 48-pin tssop 0 to +70c 9fg108dgilf tubes 48-pin tssop -40 to +85c 9fg108dgilft tape and reel 48-pin tssop -40 to +85c parts that are ordered with a ?lf? suffix to the part number are the pb-free configuration and are rohs compliant.
ics9fg108d frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 18 innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support 408-284-6578 pcclockhelp@idt.com corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited prime house barnett wood lane leatherhead, surrey united kingdom kt22 7de +44 1372 363 339 ? 2009 integrated device technology , inc. all rights reserved. product specifications subject to change without notice. idt, ic s, and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa tm revision history rev. issue date description page # 0.1 12/18/2008 new datasheet. 0.2 5/7/2009 1. updated phase jitter tables. 2, updated input frequency ranges. there are now separate ranges for 14.318m input and 25m input. 3. merged i-temp and commercial temp data sheets. various a 5/14/2009 1. corrected/added tstab for industrial temperature range 2. corrected/added ref cyc- cyc jitter for industrial temperature r ange 3. move to final. 5,7 b 5/20/2009 updated ref - 14.318/25 mhz table. 7 c 11/20/2009 1. updated electical tables to clearly differentiate commercial and industrial parameter deltas. 2. changed ref load to rs = 33ohms, cl = 5pf, from cl = 30pf. slew rate limits ad j usted accordin g l y . d 12/1/2009 1. changed pull up and pull down indicators from * and ** to ^ for pull up and v for pull down. 2. corrected pin type on pin 44 from i/o to in. 2-4 e 12/16/2010 updated vdd suppl y volta g e specs 5

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